The present invention relates to a semiconductor device having a trench gate transistor and a manufacture method thereof.
Semiconductor devices have made progress very fast in density, characteristic, and the like. Among the semiconductor devices, a DRAM (Dynamic Random Access Memory) device has been remarkably advanced. Herein, it is to be noted that the DRAM device includes DRAM cells arranged in a memory cell region and peripheral circuits arranged in a peripheral region.
In such a DRAM device, the degree of integration of semiconductor elements, namely, DRAM cells has been increased substantially twice every one or two year. In order to achieve such high integration, the sizes of MOS (Metal-Oxide-Semiconductor) transistors have also been reduced. Such size reduction has entailed notable short-channel effects in the MOS transistors (hereafter, the term “transistor” would be simply abbreviated to “Tr”).
In a large-capacity DRAM device, requirements have been made not only about reducing dimensions of memory cells but also about making the channel length of each transfer gate Tr short. Otherwise, the performance of the transfer gate Tr is deteriorated and, as a result, problems take place about deterioration in the retention or write characteristic of the DRAM memory cells. In the following description, the term “the transfer gate Tr of the memory cell” would be referred to as the “memory cell Tr”.
As one of countermeasures against the short-channel effects in the memory cell Tr's, trench gate Tr's have been developed in which channels are formed in a three-dimensional structure. In such a trench gate Tr, a groove is formed in a semiconductor substrate and three-dimensional groove boundaries are used as channels to increase the channel length. A description will be made about a DRAM device using such trench gate Tr's (also referred to as RCAT (Recess Channel Access Transistors)), with reference to FIGS. 1 to 3.
Herein, it is to be noted that the DRAM device includes not only the memory cell Tr's but also peripheral circuit Tr's arranged in a peripheral circuit region adjacent to a memory cell region and both the memory cell Tr's and the peripheral circuit Tr's are manufactured in the same processes. Taking this into account, the following description will be directed to both the memory cell Tr′ and the peripheral circuit Tr's for an understanding of the present invention.
FIG. 1 is a plan view of memory cell Tr's of the DRAM device, FIG. 2 is a plan view of peripheral circuit Tr's, and FIG. 3 is a cross-sectional view of the memory cell taken along line A-A′ of FIG. 1.
As shown in FIG. 1, a plurality of active regions 1 are obliquely arranged and 2-bit memory cells are placed in each one active region 1. Thus, one-bit cell region has an area of 6F2. Specifically, a bit line contact is formed at a central part of each active region 1 and is connected to both a bit line 6 and a drain region formed in each active region. Source regions are formed in each active region on both sides of the bit line contact to provide two memory cell Tr's and are connected to capacitors through substrate contacts 5. A multiplicity of memory cells are repeatedly arranged in matrix while using in common bit lines 6 arranged transversely (in the X direction) and word lines (including gate electrodes) 2 arranged vertically (in the Y direction).
As shown in FIG. 1, an epitaxial layer 3 is selectively formed on a substrate surface defining the sources and the drains, and LDD side walls 4 are formed on side walls of each word line 2.
On the other hand, each of the peripheral circuit Tr's shown in FIG. 2 has, in the active regions 1, a word line 2 defining a gate electrode and source and drain diffusion layer regions. An epitaxial layer 3 is deposited on the diffusion layers. The diffusion layers are connected to other elements through substrate contacts 8 on the epitaxial layer 3. LDD side walls 4 are formed on the side walls of the word line 2.
Next, description will be made about a trench gate Tr that is shown in FIG. 3 and that is included in each memory cell. The illustrated memory cell has an isolation insulation film 10 for trench isolation, a groove 11, a gate oxide film 12, a gate electrode 13, a first conductive film layer 14 in the substrate contact, a low-concentration impurity diffusion layer 15, a high-concentration impurity diffusion layer 16, an insulation film mask (SiN, Al2O3 film) 17 on the gate electrode 13, a second conductive film layer 19 in the substrate contact, and a gate electrode side wall oxide film 20.
The trench gate Tr is capable of suppressing the short-channel effects of the Tr by forming the Tr channel part into a groove shape to increase the effective distance between the source and drain of the Tr. In this configuration of the trench gate Tr, however, an opposing area between the gate electrode 13 and the substrate becomes wide. This in turn increases the parasitic capacitance of the word line 2, entailing a problem of deterioration in its rise characteristics when the potential is turned ON. In some cases, the number of memory cells connected to each word line 2 must be reduced (that is, the length of each word line must be reduced), which results in an increase of a chip size.
Japanese Laid-Open Patent Publication No. 2004-95745 (Document D1) discloses a trench access transistor (TAT) which embeds a word line in a substrate. The trench access transistor disclosed in Document D1 has a trench and comprises a gate insulation film and a lower gate electrode formed on the gate insulation film in the trench. Specifically, the lower gate electrode is formed by a first conductive layer and a second gate electrode partially buried in the first conductive layer and partially projected from a top surface of the first gate electrode. Both the first and the second gate electrodes act as the word line buried in the substrate. In addition, a silicide layer is formed on the second gate electrode and is surrounded by a side wall insulator layer. Specifically, the first conductive layer is etched to a depth lower than the surface of the second conductive layer, whereby a groove is formed. The side wall insulator layer is formed in the groove, and the silicide layer is formed as an upper gate electrode. This configuration ensures a distance between the upper gate electrode and the gate insulation film. Moreover, the trench access transistor further has a channel diffusion layer under the bottom of the trench to provide a channel.
However, the trench access transistor disclosed in Document D1 is very complicate in structure and has a two-dimensional channel region. This is because the channel diffusion layer is confined under the bottom of the trench alone in Document D1.
Alternatively, Japanese Laid-Open Patent Publication No. 2005-354069 (Document D2) proposes an RCAT (Recess-Channel-Array Transistor), which has a channel defined by the groove formed in a substrate.
However, Document D2 neither teaches any problem entailing the RCAT nor discloses means for solving the problems of the RCAT.